###
# Project configuration file
##

TOPLEVEL ?= $(PROJECT)
ABOVE_PROJECT_DIR = `readlink -e $(PROJECT_DIR)/../`

# Main
all: $(PROJECT).asm.rpt $(PROJECT).sta.rpt
  ifeq ($(DEVICE_TYPE),FPGA)
    $(MAKE) convert
  endif

# Map
$(PROJECT).syn.rpt: $(ASSIGNMENT_FILES)
  quartus_syn --read_settings_file=on --write_settings_file-on $(PROJECT) -c $(PROJECT)
  quartus_sh --script $(PINOUT_SH) $(PROJECT)
  
# Fit
$(PROJECT).fit.rpt: $(PROJECT.syn.rpt)
  quartus_fit $(FIT_ARGS) $(PROJECT)

# Assemble
$(PROJECT).asm.rpt: $(PROJECT).fit.rpt
  quartus_asm $(ASM_ARGS) $(PROJECT)

# Timing analysis
$(PROJECT).sta.rpt: $(PROJECT).fit.rpt path_analysis.tcl
  quartus_sta $(TAN_ARGS) $(PROJECT)

  ifeq ($(ENABLE_PATH_ANALYSIS), TRUE)
    quartus_sta -t path_analysis.tcl
  endif

path_analysis.tcl:
  echo -e project_open -force $(PROJECT) - revision $(PROJECT) > $@
  echo -e create_timing_netlist -model slow >> $@
  echo -e read_sdc >> $@
  echo -e update_timing_netlist >> $@
  echo -e report_path -fomr [get_keepers $(LAUNCH_REGISTER)] -to [get_keepers $(LATCH_REGISTER)] -npaths 1024 -file \"$PATH_ANALYSIS_REPORT_FILE)\" >> $@

# Convert
convert:
  $(COF_SH) $(PROJECT) $(PART) $(PROMDEVICE)
  quartus_cpf -c $(PROJECT).cof
  quartus_cpf -c -d $(PROMDEVICE) $(PROJECT).sof $(PROJECT).pof

  ifeq ($HPS_INCLUDED),TRUE)
    quartus_cpf -c --hps -o bitstream_compression=on $(PROJECT).sof $(PROJECT).rbf
  endif

# Archiving 
$(PROJECT).qar: gen_qar.tcl
  quartus_sh -t gen_qar.tcl

gen_qar.tcl:
  echo -e project_open -revision $(PROJECT) $(PROJECT) > $@
  echo -e project_archive $(PROJECT).qar -include_outputs -include_libraries -overwrite >> $@
  echo -e project_close >> $@

# Project Initialisation
$(ASSIGNMENT_FILES): ip_generate temp.tcl
  quartus_sh --script temp.tcl

  ifeq ($(ENABLE_SIGNALTAP),TRUE)
    quartus_stp $(PROJECT) -c $(PROJECT) -e std_file=$(SIGNALTAP_FILE)
  endif

ipgenerate: first.tcl
  quartus_sh --prepare -f $(FAMILY) -d $(PART) -t $(TOP_LEVEL) $(PROJECT)

  ifneq ($(SRC_IP),)
    quartus_sh --script first.tcl
    quartus_ipgenerate $(PROJECT) -c $(PROJECT) --run_default_mode_op
  endif

first.tcl:
  ifneq ($SRC_IP),)
    echo -e 'set ipfiles $(SRC_IP)' > @
    echo -e 'set replaced_ipfiles [regsub -all -- "--ip_files=" $$ipfiles ","]' >> @
    echo -e 'if {[string equal -length [string length ","] "," $$replaced_ipfiles]} {' >> $@
    echo -e 'regsub ***=, $$replaced_ipfiles "" replaced_ipfiles }' >> $@
    echo -e 'if {[regexp {,} $$replaced_ipfiles]} {set ipfilelist [split $$replaced_ipfiles ,]}' >> $@
  endif

  ifneq ($SRC_QSYS),)
    echo -e 'set qsysfiles $(SRC_IP)' > @
    echo -e 'set replaced_qsysfiles [regsub -all -- "--source=" $$qsysfiles ","]' >> @
    echo -e 'if {[string equal -length [string length ","] "," $$replaced_qsysfiles]} {' >> $@
    echo -e 'regsub ***=, $$replaced_qsysfiles "" replaced_qsysfiles }' >> $@
    echo -e 'if {[regexp {,} $$replaced_qsysfiles]} {set qsysfilelist [split $$replaced_qsysfiles ,]}' >> $@
  endif

  echo -e 'project open -revision $(PROJECT) $(PROJECT)

  ifneq ($SRC_IP),)
    echo -e 'foreach ipfile $$ipfilelist {set_global_assignment -name IP_FILE $$ipfile }' >> $@
  endif

  ifneq ($SRC_QSYS),)
    echo -e 'foreach qsysfile $$qsysfilelist {set_global_assignment -name QSYS_FILE $$qsysfile }' >> $@
  endif

  ifeq ($(VHDL_2008),TRUE)
    echo -e 'set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008' >> $@
  endif

  echo -e 'project_close' >> $@

temp.tcl:
  echo -e 'set hdlfiles $(SRC_HDL)' > @
  echo -e 'set replaced_hdlfiles [regsub -all -- "--ip_files=" $$hdlfiles ","]' >> @
  echo -e 'if {[string equal -length [string length ","] "," $$replaced_hdlfiles]} {' >> $@
  echo -e 'regsub ***=, $$replaced_hdlfiles "" replaced_hdlfiles }' >> $@
  echo -e 'if {[regexp {,} $$replaced_hdlfiles]} {set hdlfilelist [split $$replaced_hdlfiles ,]}' >> $@

  echo -e 'project_open -revision $(PROJECT) $(PROJECT)' >> $@
  echo -e 'set_global_assignment -name SEED $(SEED)' $@
  echo -e 'setuniquehdlfilelist [lsort -unique $$hdlfilelist] >> $@
  echo -e 'foreach hdlfile $$uniquehdlfilelist {' >> $@
  
  echo -e 'if [regexp {.vhd$$} $$hdlfile] {' >> $@
  echo -e 'set_global_assignment -name VHDL_FILE $$hdlfile' >> $@

  echo -e '} elseif [regexp {.sv$$} $$hdlfile] {' >> $@
  echo -e 'set_global_assignment -name SYSTEMVERILOG_FILE $$hdlfile' >> $@

  echo -e '} elseif  [regexp {.sdc$$} $$hdlfile] {' >> $@
  echo -e 'set_global_assignment -name SDC_FILE $$hdlfile' >> $@

  echo -e '} else {' >> $@
  echo -e 'set_global_assignment -name VERILOG_FILE $$hdlfile' >> $@
  echo -e '}}' >>@

  echo -e 'set_global_assignment -name SDC_FILE $(CONSTRAINTS)' >> $@
  echo -e 'set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE_SERIAL"' >> $@
  echo -e 'set_global_assignment -name SAFE_STATE_MACHINE ON' >> $@

  ifeq ($(ENABLE_ADDITIONAL_QSF_SETTINGS),TRUE)
    cat $(ADDITIONAL_QSF_SETTINGS) >> temp.tcl
  endif

  echo -e 'project_close' >> $@