-- This file is a wrapper for the LSFR variants so that they can be tested properly using the testbenching methods
-- This wrapper is not meant to see use outside of simulation

-- The ports are as follows:
-- clk    - Input port for a clocking signal
-- rst    - Input port for a reset signal. Synchronous
-- en     - Enables the specific entity being tested. Follows the size port
-- mode   - This will determine the architecture being tested. 0 for fibonacci, 1 for galois
-- size   - This determines which lfsr we are looking at in terms of taps
-- seed   - This is used to set the seed in the entityies
-- output - This outputs the PRBS values generated  by the LFSR under test 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lfsr_test_wrapper is
  generic
  (
    SIZE : natural := 32
  );
  port
  (
    clk  : in  std_logic;
    rst  : in  std_logic;
    seed : in  std_logic_vector(SIZE - 1 downto 0);

    lfsr_enable : in  std_logic;
    lfsr_output : out std_logic_vector(SIZE - 1 downto 0) 
  );
end entity;

architecture tb of lfsr_test_wrapper is 

begin

  lfsr_i : entity work.lfsr
  generic map
  (
    SIZE => SIZE
  )
  port map
  (
    clk => clk,
    rst => rst,
    en  => lfsr_enable,

    seed   => seed,
    output => lfsr_output
  );

end tb;