-- This component is designed to have it's output stream size set at compilation and provide PRBS values appropriate for
-- the size defined.
-- You can seed this PRBS generator by changing the value of the seed port while in reset
-- This design follows that of a fibonacci linear feedback shift register

-- The generics are as follows:
-- SIZE - This denotes the size of the output vector. This also effects the size of the seed, and the placement of taps in
--        the component

-- The ports are as follows:
-- clk    - Input port for the clocking signal
-- rst    - Input port for the reset signal. Should be synchronous.
-- en     - The enable port. The compoent will only output new data when this is high
-- seed   - This input is the starting value of the PRBS generator when reset is enabled. It will affect subsequent outputs
-- output - This output is PBRS value generated by the componet. It will change every cycle if enable is high

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.lfsr_package.all;

entity lfsr is
  generic
  (
    SIZE : natural := 128
  );
  port
  (
    clk : in  std_logic;
    rst : in  std_logic;
    en  : in  std_logic;

    seed   : in  std_logic_vector(SIZE - 1 downto 0);
    output : out std_logic_vector(SIZE - 1 downto 0) 
  );
end entity;

architecture rtl of lfsr is
  -- signals
  signal shift_register : std_logic_vector(SIZE - 1 downto 0);
  signal feedback_in    : std_logic;
  signal feedback_out   : std_logic_vector(0 to (number_of_taps(SIZE) - 1));

begin

  shift_register_proc : process (clk)
  begin
    if rising_edge(clk) then
      if en = '1' then
        shift_register(SIZE - 1 downto 1) <= shift_register(SIZE - 2 downto 0);
        shift_register(0)                 <= feedback_in;
      end if;

      if rst = '1' then
        shift_register <= seed;
      end if;
    end if;
  end process;

  feedback_calc_gen : for i in 1 to (number_of_taps(SIZE) - 1) generate
    feedback_out(i) <= shift_register(tap_position(SIZE, i + 1) - 1) xor feedback_out(i - 1);
  end generate;

  feedback_out(0) <= shift_register(SIZE - 1);
  feedback_in     <= feedback_out(number_of_taps(SIZE) - 1);

  output <= shift_register;  

end rtl;