23 lines
704 B
Makefile
23 lines
704 B
Makefile
# Default the chosen language to VHDL
|
|
TOPLEVEL_LANG ?= vhdl
|
|
|
|
# Default the sim tool to GHDL
|
|
SIM ?= ghdl
|
|
|
|
# Find the common_make_lists list that points to all the artifacts
|
|
PROJECT_DIR = ../../../
|
|
include $(PROJECT_DIR)../fpga/common_make_lists.mk
|
|
|
|
PWD=$(shell pwd)
|
|
|
|
# The location of the VHDL files that will be used in the sim
|
|
SOURCE_FILES = $(abspath $(LFSR_TB_SRC))
|
|
|
|
# Formatting all the source files correctly to input into the simulation
|
|
VHDL_SOURCES = $(shell echo '$(SOURCE_FILES)' | tr " " "\n" | awk '!x[$$0]++' | tr "\n" " ")
|
|
|
|
TOPLEVEL = lfsr_test_wrapper
|
|
MODULE := lfsr_test_suite
|
|
|
|
include $(shell cocotb-config --makefiles)/Makefile.inc
|
|
include $(shell cocotb-config --makefiles)/Makefile.sim |