52 lines
1.3 KiB
VHDL
52 lines
1.3 KiB
VHDL
-- This file is a wrapper for the LSFR variants so that they can be tested properly using the testbenching methods
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-- This wrapper is not meant to see use outside of simulation
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-- The ports are as follows:
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-- clk - Input port for a clocking signal
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-- rst - Input port for a reset signal. Synchronous
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-- en - Enables the specific entity being tested. Follows the size port
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-- mode - This will determine the architecture being tested. 0 for fibonacci, 1 for galois
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-- size - This determines which lfsr we are looking at in terms of taps
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-- seed - This is used to set the seed in the entityies
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-- output - This outputs the PRBS values generated by the LFSR under test
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lfsr_test_wrapper is
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generic
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(
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SIZE : natural := 32
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);
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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seed : in std_logic_vector(SIZE - 1 downto 0);
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lfsr_enable : in std_logic;
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lfsr_output : out std_logic_vector(SIZE - 1 downto 0)
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);
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end entity;
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architecture tb of lfsr_test_wrapper is
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begin
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lfsr_i : entity work.lfsr
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generic map
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(
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SIZE => SIZE
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)
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port map
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(
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clk => clk,
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rst => rst,
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en => lfsr_enable,
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seed => seed,
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output => lfsr_output
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);
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end tb; |