99 lines
2.2 KiB
VHDL
99 lines
2.2 KiB
VHDL
-- This component is designed to have it's output stream size set at compilation and provide PRBS values appropriate for
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-- the size defined.
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-- You can seed this PRBS generator by changing the value of the seed port while in reset
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-- This design follows that of a fibonacci linear feedback shift register
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-- The generics are as follows:
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-- SIZE - This denotes the size of the output vector. This also effects the size of the seed, and the placement of taps in
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-- the component
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-- The ports are as follows:
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-- clk - Input port for the clocking signal
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-- rst - Input port for the reset signal. Should be synchronous.
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-- en - The enable port. The compoent will only output new data when this is high
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-- seed - This input is the starting value of the PRBS generator when reset is enabled. It will affect subsequent outputs
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-- output - This output is PBRS value generated by the componet. It will change every cycle if enable is high
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.lfsr_package.all;
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entity lfsr is
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generic
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(
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SIZE : natural := 128
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);
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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en : in std_logic;
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seed : in std_logic_vector(SIZE - 1 downto 0);
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output : out std_logic_vector(SIZE - 1 downto 0)
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);
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end entity;
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architecture rtl of lfsr is
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-- signals
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signal shift_register : std_logic_vector(SIZE - 1 downto 0);
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signal feedback_in : std_logic;
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signal feedback_out : std_logic_vector(0 to (number_of_taps(SIZE) - 1));
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begin
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shift_register_proc : process (clk)
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begin
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if rising_edge(clk) then
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if en = '1' then
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shift_register(SIZE - 1 downto 1) <= shift_register(SIZE - 2 downto 0);
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shift_register(0) <= feedback_in;
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end if;
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if rst = '1' then
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shift_register <= seed;
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end if;
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end if;
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end process;
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feedback_calc_gen : for i in 1 to (number_of_taps(SIZE) - 1) generate
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feedback_out(i) <= shift_register(tap_position(SIZE, i + 1) - 1) xor feedback_out(i - 1);
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end generate;
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feedback_out(0) <= shift_register(SIZE - 1);
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feedback_in <= feedback_out(number_of_taps(SIZE) - 1);
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output <= shift_register;
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end rtl;
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